94 search results - page 16 / 19 » Exploiting Speculative Thread-Level Parallelism on a SMT Pro... |
IISWC
2009
IEEE
14 years 3 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
ASPLOS
2011
ACM
13 years 4 days ago
2011
ACM
Multicore processors have become ubiquitous in today’s systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications ...
ICPP
2008
IEEE
14 years 3 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
ICS
2005
Tsinghua U.
14 years 2 months ago
2005
Tsinghua U.
Given the importance of parallel mesh generation in large-scale scientific applications and the proliferation of multilevel SMTbased architectures, it is imperative to obtain ins...
CASES
2003
ACM
14 years 1 months ago
2003
ACM
The proliferation of computing technology to low power domains such as hand–held devices has lead to increased interest in portable interface technologies, with particular inter...