Sciweavers

110 search results - page 3 / 22
» Exploiting Vector Parallelism in Software Pipelined Loops
Sort
View
ICPP
2002
IEEE
14 years 14 days ago
Optimal Code Size Reduction for Software-Pipelined Loops on DSP Applications
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...
Qingfeng Zhuge, Zili Shao, Edwin Hsing-Mean Sha
EUROPAR
2006
Springer
13 years 11 months ago
Multi-dimensional Kernel Generation for Loop Nest Software Pipelining
Single-dimension Software Pipelining (SSP) has been proposed as an effective software pipelining technique for multi-dimensional loops [16]. This paper introduces for the first tim...
Alban Douillet, Hongbo Rong, Guang R. Gao
CC
2003
Springer
14 years 23 days ago
Early Control of Register Pressure for Software Pipelined Loops
Abstract. The register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation at firs...
Sid Ahmed Ali Touati, Christine Eisenbeis
ISSS
2002
IEEE
154views Hardware» more  ISSS 2002»
14 years 13 days ago
Optimal Code Size Reduction for Software-Pipelined and Unfolded Loops
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
Bin Xiao, Zili Shao, Chantana Chantrapornchai, Edw...
PLDI
2000
ACM
13 years 12 months ago
Exploiting superword level parallelism with multimedia instruction sets
Increasing focus on multimedia applications has prompted the addition of multimedia extensions to most existing general purpose microprocessors. This added functionality comes pri...
Samuel Larsen, Saman P. Amarasinghe