110 search results - page 5 / 22 » Exploiting Vector Parallelism in Software Pipelined Loops |
PPOPP
2010
ACM
14 years 4 months ago
2010
ACM
Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memo...
HPCA
1996
IEEE
13 years 11 months ago
1996
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
EMSOFT
2004
Springer
14 years 28 days ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
CGO
2009
IEEE
14 years 2 months ago
2009
IEEE
—The StreamIt programming model has been proposed to exploit parallelism in streaming applications on general purpose multicore architectures. This model allows programmers to sp...
TCAD
2008
13 years 7 months ago
2008
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...