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» Exploiting loop-dependent stream reuse for stream processors
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CF
2005
ACM
13 years 9 months ago
Exploiting temporal locality in drowsy cache policies
Technology projections indicate that static power will become a major concern in future generations of high-performance microprocessors. Caches represent a significant percentage ...
Salvador Petit, Julio Sahuquillo, Jose M. Such, Da...
ASPLOS
2009
ACM
14 years 8 months ago
Architectural support for SWAR text processing with parallel bit streams: the inductive doubling principle
Parallel bit stream algorithms exploit the SWAR (SIMD within a register) capabilities of commodity processors in high-performance text processing applications such as UTF8 to UTF-...
Robert D. Cameron, Dan Lin
FCCM
2003
IEEE
123views VLSI» more  FCCM 2003»
14 years 29 days ago
FPGA-based SIMD Processor
A massively parallel single instruction multiple data stream (SIMD) processor designed specifically for cryptographic key search applications is presented. This design aims to ex...
Stanley Y. C. Li, Gap C. K. Cheuk, Kin-Hong Lee, P...
IPPS
1996
IEEE
13 years 11 months ago
A Memory Controller for Improved Performance of Streamed Computations on Symmetric Multiprocessors
The growing disparity between processor and memory speeds has caused memory bandwidth to become the performance bottleneck for many applications. In particular, this performance g...
Sally A. McKee, William A. Wulf
ASPDAC
2010
ACM
143views Hardware» more  ASPDAC 2010»
13 years 5 months ago
Constrained global scheduling of streaming applications on MPSoCs
Abstract-- We present a global scheduling framework for synchronous data flow (SDF) streaming applications on MPSoCs, based on optimized computation and contention-free routing. Th...
Jun Zhu, Ingo Sander, Axel Jantsch