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ICESS
2007
Springer
14 years 1 months ago
Handling Control Data Flow Graphs for a Tightly Coupled Reconfigurable Accelerator
In an embedded system including a base processor integrated with a tightly coupled accelerator, extracting frequently executed portions of the code (hot portion) and executing thei...
Hamid Noori, Farhad Mehdipour, Morteza Saheb Zaman...
ICMCS
2006
IEEE
146views Multimedia» more  ICMCS 2006»
14 years 1 months ago
Collaborative Multithreading: An Open Scalable Processor Architecture for Embedded Multimedia Applications
Numerous approaches can be employed in exploiting computation power in processors such as superscalar, VLIW, SMT and multi-core on chip. In this paper, a UniCore VisoMT processor ...
Wei-Chun Ku, Shu-Hsuan Chou, Jui-Chin Chu, Chih-He...
INFOCOM
2007
IEEE
14 years 2 months ago
End-to-End Routing for Dual-Radio Sensor Networks
— Dual-radio, dual-processor nodes are an emerging class of Wireless Sensor Network devices that provide both lowenergy operation as well as substantially increased computational...
Thanos Stathopoulos, Martin Lukac, Dustin McIntire...
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 2 months ago
Operating System Controlled Processor-Memory Bus Encryption
—Unencrypted data appearing on the processor– memory bus can result in security violations, e.g., allowing attackers to gather keys to financial accounts and personal data. Al...
Xi Chen, Robert P. Dick, Alok N. Choudhary
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
14 years 1 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...