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VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
14 years 9 months ago
Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
M. S. Gaur, Mark Zwolinski
IUI
2009
ACM
14 years 5 months ago
You can play that again: exploring social redundancy to derive highlight regions in videos
Identifying highlights in multimedia content such as video and audio is currently a very difficult technical problem. We present and evaluate a novel algorithm that identifies hig...
Jose San Pedro, Vaiva Kalnikaité, Steve Whi...
VL
2008
IEEE
130views Visual Languages» more  VL 2008»
14 years 3 months ago
Exploring the evolution of software quality with animated visualization
Assessing software quality and understanding how events in its evolution have lead to anomalies are two important steps toward reducing costs in software maintenance. Unfortunatel...
Guillaume Langelier, Houari A. Sahraoui, Pierre Po...
IPPS
2007
IEEE
14 years 3 months ago
Exploring a Multithreaded Methodology to Implement a Network Communication Protocol on the Cyclops-64 Multithreaded Architecture
The IBM Cyclops-64 (C64) chip employs a multithreaded architecture that integrates a large number of hardware thread units on a single chip. A cellular supercomputer is being deve...
Ge Gan, Ziang Hu, Juan del Cuvillo, Guang R. Gao
DSN
2006
IEEE
14 years 3 months ago
Exploring Fault-Tolerant Network-on-Chip Architectures
The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are ...
Dongkook Park, Chrysostomos Nicopoulos, Jongman Ki...