1497 search results - page 68 / 300 » Extended static checking |
DAC
2007
ACM
14 years 10 months ago
2007
ACM
The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part of nanometer VLSI design. Under the context of ti...
CODES
2008
IEEE
14 years 3 months ago
2008
IEEE
Processor Idle Cycle Aggregation (PICA) is a promising approach for low power execution of processors, in which small memory stalls are aggregated to create a large one, and the p...
GLVLSI
2006
IEEE
14 years 3 months ago
2006
IEEE
Process technology and environment-induced variability of gates and wires in VLSI circuits make timing analyses of such circuits a challenging task. Process variation can have a s...
MICRO
1991
IEEE
14 years 15 days ago
1991
IEEE
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
TON
2002
13 years 8 months ago
2002
We present two routing strategies, identified herein as static least loaded routing (SLLR) and dynamic least loaded routing (DLLR). Dynamic routing in circuit-switched networks has...