Sciweavers

157 search results - page 16 / 32
» Extending Symmetry Reduction by Exploiting System Architectu...
Sort
View
ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
14 years 1 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
GLOBECOM
2006
IEEE
14 years 1 months ago
Honeycomb Architecture for Energy Conservation in Wireless Sensor Networks
— Reducing energy consumption has been a recent focus of wireless sensor network research. Topology control explores the potential that a dense network has for energy savings. On...
Ren Ping Liu, Glynn Rogers, Sihui Zhou
RTAS
2008
IEEE
14 years 2 months ago
Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures
Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues p...
Jack Whitham, Neil C. Audsley
GI
2004
Springer
14 years 1 months ago
Dynamical Vertical Integration of Distributed Java Components Using an Architecture Model
Abstract: A key idea of architecture is the description of components and their connections. This information can be extended to define the horizontal and vertical distribution of...
Alexander Prack, Ulf Schreier
ISCA
1999
IEEE
94views Hardware» more  ISCA 1999»
14 years 1 hour ago
A Performance Comparison of Contemporary DRAM Architectures
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-bas...
Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor ...