157 search results - page 5 / 32 » Extending Symmetry Reduction by Exploiting System Architectu... |
VLSID
1997
IEEE
13 years 12 months ago
1997
IEEE
I n this paper, we first present a pipelined delayed least mean square (DLMS) adaptive filter architecture whose power dissipation meets a specified budget. This low-power archite...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been...
CASES
2009
ACM
13 years 11 months ago
2009
ACM
2's complement number system imposes a fundamental limitation on the power and performance of arithmetic circuits, due to the fundamental need of cross-datapath carry propaga...
LCTRTS
1999
Springer
13 years 12 months ago
1999
Springer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
ATAL
2005
Springer
14 years 1 months ago
2005
Springer
We present here Extended Markov Tracking (EMT), a computationally tractable method for the online estimation of Markovian system dynamics, along with experimental support for its ...