157 search results - page 9 / 32 » Extending Symmetry Reduction by Exploiting System Architectu... |
CORR
2011
Springer
12 years 11 months ago
2011
Springer
The Model Checking Integrated Planning System (MIPS) has shown distinguished performance in the second and third international planning competitions. With its object-oriented fram...
CGO
2010
IEEE
14 years 2 months ago
2010
IEEE
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM T...
SBACPAD
2007
IEEE
14 years 1 months ago
2007
IEEE
One way to exploit Thread Level Parallelism (TLP) is to use architectures that implement novel multithreaded execution models, like Scheduled DataFlow (SDF). This latter model pro...
IEEEPACT
1999
IEEE
13 years 12 months ago
1999
IEEE
Increases in instruction level parallelism are needed to exploit the potential parallelism available in future wide issue architectures. Predicated execution is an architectural m...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various ...