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ARC
2007
Springer
150views Hardware» more  ARC 2007»
13 years 11 months ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
FPL
2007
Springer
99views Hardware» more  FPL 2007»
13 years 11 months ago
Disjoint Pattern Enumeration for Custom Instructions Identification
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. These custom instructions are selected through an analys...
Pan Yu, Tulika Mitra
ARC
2006
Springer
157views Hardware» more  ARC 2006»
13 years 11 months ago
PISC: Polymorphic Instruction Set Computers
We introduce a new paradigm in the computer architecture referred to as Polymorphic Instruction Set Computers (PISC). This new paradigm, in difference to RISC/CISC, introduces hard...
Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Won...
EDBTW
2006
Springer
13 years 11 months ago
Implementing a Linguistic Query Language for Historic Texts
Abstract. We describe design and implementation of the linguistic query language DDDquery. This language aims at querying a large linguistic database storing a corpus of richly ann...
Lukas Faulstich, Ulf Leser, Thorsten Vitt
EMSOFT
2006
Springer
13 years 11 months ago
A hierarchical coordination language for interacting real-time tasks
We designed and implemented a new programming language called Hierarchical Timing Language (HTL) for hard realtime systems. Critical timing constraints are specified within the la...
Arkadeb Ghosal, Alberto L. Sangiovanni-Vincentelli...