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SP
2009
IEEE
143views Security Privacy» more  SP 2009»
14 years 3 months ago
Practical Mitigations for Timing-Based Side-Channel Attacks on Modern x86 Processors
—This paper studies and evaluates the extent to which automated compiler techniques can defend against timing-based side-channel attacks on modern x86 processors. We study how mo...
Bart Coppens, Ingrid Verbauwhede, Koen De Bosscher...
ICCS
2009
Springer
14 years 3 months ago
Generating Empirically Optimized Composed Matrix Kernels from MATLAB Prototypes
The development of optimized codes is time-consuming and requires extensive architecture, compiler, and language expertise, therefore, computational scientists are often forced to ...
Boyana Norris, Albert Hartono, Elizabeth R. Jessup...
DATE
2008
IEEE
114views Hardware» more  DATE 2008»
14 years 3 months ago
Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors
—The contribution of memory latency to execution time continues to increase, and latency hiding mechanisms become ever more important for efficient processor design. While high-...
Sanghyun Park, Aviral Shrivastava, Yunheung Paek
GLVLSI
2008
IEEE
112views VLSI» more  GLVLSI 2008»
14 years 3 months ago
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
Maziar Goudarzi, Tohru Ishihara
SAINT
2006
IEEE
14 years 2 months ago
A Pervasive Internet Approach to Fine-Grain Power-Aware Computing
We present a novel approach to conserve power in networked mobile devices. Our approach exploits communication within a pervasive smart space as an opportunity to save power as op...
Ahmed Abukmail, Abdelsalam Helal