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ICS
2001
Tsinghua U.
14 years 1 months ago
Global optimization techniques for automatic parallelization of hybrid applications
This paper presents a novel technique to perform global optimization of communication and preprocessing calls in the presence of array accesses with arbitrary subscripts. Our sche...
Dhruva R. Chakrabarti, Prithviraj Banerjee
COLING
1996
13 years 10 months ago
Computing Phrasal-signs in HPSG prior to Parsing
This t)ai)er deseril)es techniques to compile lexical entries in IIPSG (Pollard and
Kentaro Torisawa, Jun-ichi Tsujii
DATE
2005
IEEE
115views Hardware» more  DATE 2005»
14 years 2 months ago
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs
This paper presents an infrastructure to test the functionality of the specific architectures output by a highlevel compiler targeting dynamically reconfigurable hardware. It resu...
Rui Rodrigues, João M. P. Cardoso
HOTOS
2003
IEEE
14 years 1 months ago
Cassyopia: Compiler Assisted System Optimization
Execution of a program almost always involves multiple address spaces, possibly across separate machines. Here, an approach to reducing such costs using compiler optimization tech...
Mohan Rajagopalan, Saumya K. Debray, Matti A. Hilt...
EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
14 years 5 days ago
Use of embedded scheduling to compile VHDL for effective parallel simulation
This paper describes VHDL compilation techniques, embodied in the Auriga compiler [3,14], which facilitate parallel or distributed simulation by embedding evaluation scheduling in...
John Willis, Zhiyuan Li, Tsang-Puu Lin