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DATE
2003
IEEE
97views Hardware» more  DATE 2003»
14 years 3 months ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
ISADS
2003
IEEE
14 years 3 months ago
A GUI Approach to Programming of TMO Frames and Design of Real-Time Distributed Computing Software
An advanced high-level approach for programming of real-time distributed computing applications, the TMO (Time-triggered Message-triggered Object) programming and specification sc...
K. H. Kim, Seok-Joong Kang
WCRE
2003
IEEE
14 years 3 months ago
An Experimentation Framework for Evaluating Disassembly and Decompilation Tools for C++ and Java
The inherent differences between C++ and Java programs dictate that the methods used for reverse engineering their compiled executables will be languagespecific. This paper looks ...
Lori Vinciguerra, Linda M. Wills, Nidhi Kejriwal, ...
WORDS
2003
IEEE
14 years 3 months ago
Middleware Support for Embedded Software with Multiple QoS Properties for Ubiquitous Computing Environments
Ubiquitous application software usually has multiple QoS requirements, such as situationawareness, real-time, and security, which make the application software development complic...
Stephen S. Yau, Yu Wang, Dazhi Huang
PLDI
2003
ACM
14 years 3 months ago
Region-based hierarchical operation partitioning for multicluster processors
Clustered architectures are a solution to the bottleneck of centralized register files in superscalar and VLIW processors. The main challenge associated with clustered architectu...
Michael L. Chu, Kevin Fan, Scott A. Mahlke