Sciweavers

393 search results - page 11 / 79
» FIFO Communication Models in Operating Systems for Reconfigu...
Sort
View
DAC
2002
ACM
14 years 9 months ago
Dynamic hardware plugins in an FPGA with partial run-time reconfiguration
Tools and a design methodology have been developed to support partial run-time reconfiguration of FPGA logic on the Field Programmable Port Extender. High-speed Internet packet pr...
Edson L. Horta, John W. Lockwood, David E. Taylor,...
CCGRID
2007
IEEE
14 years 3 months ago
Adaptive Performance Modeling on Hierarchical Grid Computing Environments
In the past, efficient parallel algorithms have always been developed specifically for the successive generations of parallel systems (vector machines, shared-memory machines, d...
Wahid Nasri, Luiz Angelo Steffenel, Denis Trystram
RTS
2006
106views more  RTS 2006»
13 years 8 months ago
Q-SCA: Incorporating QoS support into software communications architecture for SDR waveform processing
The Software Communications Architecture (SCA) defined by Joint Tactical Radio Systems (JTRS) is the de facto standard middleware currently adopted by the Software Defined Radio (...
Jaesoo Lee, Saehwa Kim, Jiyong Park, Seongsoo Hong
SIGOPS
2011
210views Hardware» more  SIGOPS 2011»
13 years 3 months ago
Small trusted primitives for dependable systems
Secure, fault-tolerant distributed systems are difficult to build, to validate, and to operate. Conservative design for such systems dictates that their security and fault toleran...
Petros Maniatis, Byung-Gon Chun
TC
2010
13 years 3 months ago
Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization
We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator ...
Holger Lange, Andreas Koch