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» FPGA interconnect design using logical effort
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FPGA
1997
ACM
149views FPGA» more  FPGA 1997»
13 years 11 months ago
Signal Processing at 250 MHz Using High-Performance FPGA's
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
Brian Von Herzen
FPL
2000
Springer
124views Hardware» more  FPL 2000»
13 years 11 months ago
Balancing Logic Utilization and Area Efficiency in FPGAs
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
Russell Tessier, Heather Giza
FPT
2005
IEEE
163views Hardware» more  FPT 2005»
14 years 1 months ago
Designing an FPGA SoC Using a Standardized IP Block Interface
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...
FPGA
2006
ACM
116views FPGA» more  FPGA 2006»
13 years 11 months ago
Performance benefits of monolithically stacked 3D-FPGA
The performance benefits of a monolithically stacked 3DFPGA, whereby the programming overhead of an FPGA is stacked on top of a standard CMOS layer containing the logic blocks and...
Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, Simon Wo...
FPGA
1998
ACM
142views FPGA» more  FPGA 1998»
13 years 11 months ago
A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing archit...
Mohammed A. S. Khalid, Jonathan Rose