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» FPGA interconnect design using logical effort
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FPGA
2009
ACM
159views FPGA» more  FPGA 2009»
14 years 3 months ago
Choose-your-own-adventure routing: lightweight load-time defect avoidance
Aggressive scaling increases the number of devices we can integrate per square millimeter but makes it increasingly difficult to guarantee that each device fabricated has the inte...
Raphael Rubin, André DeHon
ISLPED
2005
ACM
91views Hardware» more  ISLPED 2005»
14 years 2 months ago
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
As FPGAs enter the nanometer regime, several modifications are needed to reduce the increasing leakage power dissipation. Hence, this work presents some modifications to the FPG...
Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
FPGA
2012
ACM
300views FPGA» more  FPGA 2012»
12 years 4 months ago
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
In floating-point datapaths synthesized on FPGAs, the shifters that perform mantissa alignment and normalization consume a disproportionate number of LUTs. Shifters are implemente...
Yehdhih Ould Mohammed Moctar, Nithin George, Hadi ...
FPGA
2008
ACM
146views FPGA» more  FPGA 2008»
13 years 10 months ago
FPGA-optimised high-quality uniform random number generators
This paper introduces a method of constructing random number generators from four of the basic primitives provided by FPGAs: Flip-Flips, Lookup-Tables, Shift Registers, and RAMs. ...
David B. Thomas, Wayne Luk
ASAP
2008
IEEE
146views Hardware» more  ASAP 2008»
14 years 3 months ago
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary...