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» FPGA interconnect design using logical effort
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ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
14 years 5 months ago
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
Gordon R. Chiu, Deshanand P. Singh, Valavan Manoha...
VLSISP
2011
358views Database» more  VLSISP 2011»
13 years 3 months ago
Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition
Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from superlinear increases in ...
Karthik Nagarajan, Brian Holland, Alan D. George, ...
ICASSP
2008
IEEE
14 years 3 months ago
Parameterized design framework for hardware implementation of particle filters
Particle filtering methods provide powerful techniques for solving non-linear state-estimation problems, and are applied to a variety of application areas in signal processing. Be...
Sankalita Saha, Neal K. Bambha, Shuvra S. Bhattach...
TCAD
2002
146views more  TCAD 2002»
13 years 8 months ago
Static scheduling of multidomain circuits for fast functional verification
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
Murali Kudlugi, Russell Tessier
ARITH
2007
IEEE
14 years 3 months ago
Design of the ARM VFP11 Divide and Square Root Synthesisable Macrocell
This paper presents the detailed design of the ARM VFP11 Divide and Square Root synthesisable macrocell. The macrocell was designed using the minimum-redundancy radix-4 SRT digit ...
Neil Burgess, Chris N. Hinds