87 search results - page 15 / 18 » FPGA power reduction using configurable dual-Vdd |
PACS
2000
Springer
13 years 11 months ago
2000
Springer
Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue ...
SAC
2008
ACM
13 years 7 months ago
2008
ACM
This paper proposes an address compression technique for load/store queue (LSQ) to improve the scalability and power efficiency. A load/store queue (LSQ) typically needs a fullyas...
EUROPAR
2010
Springer
13 years 7 months ago
2010
Springer
Abstract. Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the ...
CVPR
2009
IEEE
15 years 2 months ago
2009
IEEE
Local image descriptors that are highly discriminative,
computational efficient, and with low storage footprint have
long been a dream goal of computer vision research. In this
...
ICRA
2007
IEEE
14 years 1 months ago
2007
IEEE
— For certain applications, field robotic systems require small size for cost, weight, access, stealth or other reasons. Small size results in constraints on critical resources s...