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» Factoring large numbers with programmable hardware
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DATE
2002
IEEE
124views Hardware» more  DATE 2002»
14 years 21 days ago
Crosstalk Alleviation for Dynamic PLAs
—The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. Howeve...
Tzyy-Kuen Tien, Tong-Kai Tsai, Shih-Chieh Chang
SIGMETRICS
2008
ACM
128views Hardware» more  SIGMETRICS 2008»
13 years 7 months ago
Loss-aware network coding for unicast wireless sessions: design, implementation, and performance evaluation
Local network coding is growing in prominence as a technique to facilitate greater capacity utilization in multi-hop wireless networks. A specific objective of such local network ...
Shravan K. Rayanchu, Sayandeep Sen, Jianming Wu, S...
ECMDAFA
2007
Springer
122views Hardware» more  ECMDAFA 2007»
14 years 1 months ago
Model Transformation from OWL-S to BPEL Via SiTra
Although there are a large number of academic and industrial model transformation frameworks available, allowing specification, implementation, maintenance and documentation of mod...
Behzad Bordbar, Gareth Howells, Michael Evans, Ath...
CODES
2009
IEEE
13 years 11 months ago
Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhance...
Vincenzo Rana, Srinivasan Murali, David Atienza, M...
INFOCOM
2010
IEEE
13 years 6 months ago
From Time Domain to Space Domain: Detecting Replica Attacks in Mobile Ad Hoc Networks
—A common vulnerability of wireless networks, in particular, the mobile ad hoc network (MANET), is their susceptibility to node compromise/physical capture attacks since the wire...
Kai Xing, Xiuzhen Cheng