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» Factoring large numbers with programmable hardware
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DATE
2006
IEEE
114views Hardware» more  DATE 2006»
14 years 1 months ago
COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC
Memory and communication architectures have a significant impact on the cost, performance, and time-to-market of complex multi-processor system-on-chip (MPSoC) designs. The memory...
Sudeep Pasricha, Nikil D. Dutt
EGH
2003
Springer
14 years 29 days ago
Automatic shader level of detail
Current graphics hardware can render procedurally shaded objects in real-time. However, due to resource and performance limitations, interactive shaders can not yet approach the c...
Marc Olano, Bob Kuehne, Maryann Simmons
BSDCON
2003
13 years 9 months ago
ULE: A Modern Scheduler for FreeBSD
The existing thread scheduler in FreeBSD was well suited towards the computing environment that it was developed in. As the priorities and hardware targets of the project have cha...
Jeff Roberson
ICPR
2004
IEEE
14 years 8 months ago
BTF Image Space Utmost Compression and Modelling Method
The bidirectional texture function (BTF) describes texture appearance variations due to varying illumination and viewing conditions. This function is acquired by large number of m...
Jirí Filip, Michael Arnold, Michal Haindl
SIGMETRICS
2005
ACM
147views Hardware» more  SIGMETRICS 2005»
14 years 1 months ago
Denial-of-service resilience in peer-to-peer file sharing systems
Peer-to-peer (p2p) file sharing systems are characterized by highly replicated content distributed among nodes with enormous aggregate resources for storage and communication. Th...
Dan Dumitriu, Edward W. Knightly, Aleksandar Kuzma...