Sciweavers

317 search results - page 57 / 64
» Factoring logic functions using graph partitioning
Sort
View
FPL
2004
Springer
119views Hardware» more  FPL 2004»
13 years 11 months ago
Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor
Pervasive networks with low-cost embedded 8-bit processors are set to change our day-to-day life. Public-key cryptography provides crucial functionality to assure security which is...
Sandeep S. Kumar, Christof Paar
VLSISP
2008
106views more  VLSISP 2008»
13 years 7 months ago
Architecture Considerations for Multi-Format Programmable Video Processors
Many different video processor architectures exist. Its architecture gives a processor strength for a particular application. Hardwired logic yields the best performance/cost, but ...
Jonah Probell
ICFP
2008
ACM
14 years 7 months ago
From ML to MLF: graphic type constraints with efficient type inference
MLF is a type system that seamlessly merges ML-style type inference with System-F polymorphism. We propose a system of graphic (type) constraints that can be used to perform type ...
Boris Yakobowski, Didier Rémy
FSTTCS
2009
Springer
14 years 2 months ago
Modelchecking counting properties of 1-safe nets with buffers in paraPSPACE
ABSTRACT. We consider concurrent systems that can be modelled as 1-safe Petri nets communicating through a fixed set of buffers (modelled as unbounded places). We identify a param...
M. Praveen, Kamal Lodaya
DAC
1994
ACM
13 years 11 months ago
Automatic Verification of Pipelined Microprocessors
Abstract - We address the problem of automatically verifying large digital designs at the logic level, against high-level specifications. In this paper, we present a methodology wh...
Vishal Bhagwati, Srinivas Devadas