352 search results - page 35 / 71 » Fail-Awareness in Timed Asynchronous Systems |
DDECS
2009
IEEE
14 years 3 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
HICSS
1998
IEEE
14 years 1 months ago
1998
IEEE
Improvements in computer network infrastructures and information utilities have led to an increase in the number of social and work interactions carried out `virtually' by ge...
TPPP
1994
14 years 25 days ago
1994
We introduce a method for the specification of reactive asynchronous components with a concurrent access interface and outline its mathematical foundation. The method supports the...
TIME
2008
IEEE
14 years 3 months ago
2008
IEEE
In this paper we consider the specification and verification of infinite-state systems using temporal logic. In particular, we describe parameterised systems using a new variet...
RTSS
2008
IEEE
14 years 3 months ago
2008
IEEE
This paper presents the design of user-level scheduling hierarchies in the Composite component-based system. The motivation for this is centered around the design of a system that...