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» Fail-Awareness in Timed Asynchronous Systems
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MJ
2007
119views more  MJ 2007»
13 years 8 months ago
Automated energy calculation and estimation for delay-insensitive digital circuits
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, ...
ISORC
2009
IEEE
14 years 3 months ago
On the Semantics of UML/MARTE Clock Constraints
The UML goal of being a general-purpose modeling language discards the possibility to adopt too precise and strict a semantics. Users are to refine or define the semantics in th...
Frédéric Mallet, Charles André...
SASN
2003
ACM
14 years 2 months ago
Modeling vulnerabilities of ad hoc routing protocols
The purpose of this work is to automate the analysis of ad hoc routing protocols in the presence of attackers. To this end, a formal model of protocol behavior is developed in whi...
Shahan Yang, John S. Baras
SIROCCO
2010
13 years 10 months ago
Algorithms for Extracting Timeliness Graphs
We consider asynchronous message-passing systems in which some links are timely and processes may crash. Each run defines a timeliness graph among correct processes: (p, q) is an e...
Carole Delporte-Gallet, Stéphane Devismes, ...
SAS
2001
Springer
121views Formal Methods» more  SAS 2001»
14 years 1 months ago
Embedding Chaos
Model checking would answer all finite-state verification problems, if it were not for the notorious state-space explosion problem. A problem of practical importance, which attra...
Natalia Sidorova, Martin Steffen