8 search results - page 2 / 2 » Fast Cycle-accurate Behavioral Simulation for Pipelined Proc... |
HPCA
2004
IEEE
14 years 8 months ago
2004
IEEE
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
ISCA
1999
IEEE
13 years 11 months ago
1999
IEEE
Providing adequate data bandwidth is extremely important for a wide-issue superscalar processor to achieve its full performance potential. Adding a large number of ports to a data...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...