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» Fast Implementations of Automata Computations
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133
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ARITH
1999
IEEE
15 years 7 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
134
Voted
ICS
1993
Tsinghua U.
15 years 6 months ago
Anatomy of a Message in the Alewife Multiprocessor
Shared-memory provides a uniform and attractive mechanism for communication. For efficiency, it is often implemented with a layer of interpretive hardware on top of a message-pas...
John Kubiatowicz, Anant Agarwal
137
Voted
BIRTHDAY
2012
Springer
13 years 10 months ago
Masking with Randomized Look Up Tables - Towards Preventing Side-Channel Attacks of All Orders
We propose a new countermeasure to protect block ciphers implemented in leaking devices, at the intersection between One-Time Programs and Boolean masking schemes. First, we show t...
François-Xavier Standaert, Christophe Petit...
103
Voted
RT
2005
Springer
15 years 8 months ago
Radiance Cache Splatting: A GPU-Friendly Global Illumination Algorithm
Fast global illumination computation is a challenge in several fields such as lighting simulation and computergenerated visual effects for movies. To this end, the irradiance cac...
Pascal Gautron, Jaroslav Krivánek, Kadi Bou...
114
Voted
IPPS
1996
IEEE
15 years 6 months ago
Exploiting the Capabilities of Communications Co-Processors
Communications co-processors (CCPs) have become commonplace in modern MPPs and networks of workstations. These co-processors provide dedicated hardware support for fast communicat...
Klaus E. Schauser, Chris J. Scheiman, J. Mitchell ...