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CC
1998
Springer
125views System Software» more  CC 1998»
14 years 2 months ago
A New Fast Algorithm for Optimal Register Allocation in Modulo Scheduled Loops
Sylvain Lelait, Guang R. Gao, Christine Eisenbeis
ASPDAC
2005
ACM
127views Hardware» more  ASPDAC 2005»
14 years 3 months ago
Clock network minimization methodology based on incremental placement
: In ultra-deep submicron VLSI circuits, clock network is a major source of power consumption and power supply noise. Therefore, it is very important to minimize clock network size...
Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, ...
CGO
2007
IEEE
14 years 4 months ago
On the Complexity of Register Coalescing
Memory transfers are becoming more important to optimize, for both performance and power consumption. With this goal in mind, new register allocation schemes are developed, which ...
Florent Bouchez, Alain Darte, Fabrice Rastello
ASPDAC
2008
ACM
69views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Fast, quasi-optimal, and pipelined instruction-set extensions
Nowadays many customised embedded processors offer the possibility of speeding up an application by implementing it using Application-Specific Functional units (AFUs). However, th...
Ajay K. Verma, Philip Brisk, Paolo Ienne