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» Fast Path Session Creation on Network Processors
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IPPS
2005
IEEE
14 years 14 days ago
IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application
In this paper, we propose an IPSec implementation on Xilinx Virtex-II Pro FPGA1 . We move the key management and negotiation into software function calls that run on the PowerPC p...
Jing Lu, John W. Lockwood
INFOCOM
2003
IEEE
14 years 4 days ago
Load Balancing and Stability Issues in Algorithms for Service Composition
— Service composition enables flexible creation of new services by assembling independent service components. We are focused on the scenario where such composition takes place a...
Bhaskaran Raman, Randy H. Katz
APCSAC
2006
IEEE
14 years 28 days ago
Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays
Abstract. Bypass delays are expected to grow beyond 1ns as technology scales. These delays necessitate pipelining of bypass paths at processor frequencies above 1GHz and thus affe...
Lih Wen Koh, Oliver Diessel
GRID
2000
Springer
13 years 10 months ago
An Advanced User Interface Approach for Complex Parameter Study Process Specification on the Information Power Grid
The creation of parameter study suites has recently become a more challenging problem as the parameter studies have become multi-tiered and the computational environment has becom...
Maurice Yarrow, Karen M. McCann, Rupak Biswas, Rob...
ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
14 years 1 months ago
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks
— Fast addition and multiplication are of paramount importance in many arithmetic circuits and processors. The use of redundant number system for efficient implementation of thes...
Sreehari Veeramachaneni, Kirthi M. Krishna, Lingam...