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CODES
2004
IEEE
14 years 25 days ago
Automatic synthesis of system on chip multiprocessor architectures for process networks
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishna...
APSEC
2001
IEEE
14 years 23 days ago
Expert Maintainers' Strategies and Needs when Understanding Software: A Case Study Approach
Accelerating the learning curve of software maintainers working on systems with which they have little familiarity motivated this study. A working hypothesis was that automated me...
Christos Tjortjis, Paul J. Layzell
CODES
2008
IEEE
13 years 11 months ago
Slack analysis in the system design loop
We present a system-level technique to analyze the impact of design optimizations on system-level timing dependencies. This technique enables us to speed up the design cycle by su...
Girish Venkataramani, Seth Copen Goldstein
CMPB
2007
140views more  CMPB 2007»
13 years 9 months ago
Integrating digital topology in image-processing libraries
This paper describes a method to integrate digital topology informations in image processing libraries. This additional information allows a library user to write algorithms respe...
Julien Lamy
JGTOOLS
2008
98views more  JGTOOLS 2008»
13 years 9 months ago
Efficient GPU-Based Texture Interpolation using Uniform B-Splines
Abstract. This article presents uniform B-spline interpolation, completely contained on the graphics processing unit (GPU). This implies that the CPU does not need to compute any l...
Daniel Ruijters, Bart M. ter Haar Romeny, Paul Sue...