— This paper presents a number of new high-radix ripple-carry adder designs based on Ling’s addition technique and a recently-published expansion thereof. The proposed adders a...
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
—In this paper, a novel VLSI iterative divider architecture for fast quotient generation that is based on radix-2 non-restoring division is proposed. To speed up the quotient gen...
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interi...