244 search results - page 40 / 49 » Fast Set Intersection in Memory |
WWW
2008
ACM
14 years 8 months ago
2008
ACM
Supporting fast access to large RDF stores has been one of key challenges for enabling use of the Semantic Web in real-life applications, more so in sensor-based systems where lar...
WSC
1997
13 years 9 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...
SP
2008
IEEE
14 years 2 months ago
2008
IEEE
Automata-based representations and related algorithms have been applied to address several problems in information security, and often the automata had to be augmented with additi...
STOC
2006
ACM
14 years 1 months ago
2006
ACM
Memory management is a fundamental problem in computer architecture and operating systems. We consider a two-level memory system with fast, but small cache and slow, but large mai...