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FPL
2009
Springer
99views Hardware» more  FPL 2009»
14 years 10 days ago
Exploiting fast carry-chains of FPGAs for designing compressor trees
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
INFOCOM
1999
IEEE
14 years 9 hour ago
A Fast IP Routing Lookup Scheme for Gigabit Switching Routers
One of the key design issues for the new generation IP routers is the route lookup mechanism. For each incoming IP packet, the IP routing requires to perform a longest prefix match...
Nen-Fu Huang, Shi-Ming Zhao, Jen-Yi Pan, Chi-An Su
DATE
2000
IEEE
93views Hardware» more  DATE 2000»
14 years 4 days ago
Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation
In [1], Murata et al introduced an elegant representation of block placement called sequence pair. All block placement algorithms which are based on sequence pairs use simulated a...
Xiaoping Tang, D. F. Wong, Ruiqi Tian
SIGMETRICS
1994
ACM
113views Hardware» more  SIGMETRICS 1994»
13 years 11 months ago
Shade: A Fast Instruction-Set Simulator for Execution Profiling
Shade is an instruction-set simulator and custom trace generator. Application programs are executed and traced under the control of a user-supplied trace analyzer. To reduce commu...
Robert F. Cmelik, David Keppel
ICIP
2004
IEEE
14 years 9 months ago
Shear-resize factorizations for fast multi-modal volume registration
Intensity-based methods work well for multi-modal image registration owing to their effectiveness and simplicity, but the computation for geometric transforms is a heavy load. To ...
Ying Chen, Pengwei Hao, Jian Yu