522 search results - page 6 / 105 » Fast Smith-Waterman hardware implementation |
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provi...
IAJIT
2006
13 years 7 months ago
2006
In this paper, a fast hardware architecture for elliptic curve cryptography computation in Galois Field GF(p) is proposed. The architecture is implemented for 160-bits, as its dat...
ICIP
1999
IEEE
14 years 9 months ago
1999
IEEE
The Median-Rational Hybrid Filter (MRHF) has been recently introduced [1][2] as a new class of nonlinear filters and successfully applied to image filtering problems. The main cha...
CSREASAM
2009
13 years 8 months ago
2009
Tantra 1 is a novel Pseudorandom number generator (PRNG) design that provides a long sequence high quality pseudorandom numbers at very high rate both in software and hardware impl...
CODES
2004
IEEE
13 years 11 months ago
2004
IEEE
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification for fast HW/SW cosynthesis. A node in DFG represents a coarse grain block such as FIR and...