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DAC
2007
ACM
14 years 8 months ago
IPR: An Integrated Placement and Routing Algorithm
Abstract-- In nanometer-scale VLSI technologies, several interconnect issues like routing congestion and interconnect delay have become the main concerns in placement. However, all...
Min Pan, Chris C. N. Chu
ARITH
2001
IEEE
13 years 11 months ago
Computer Arithmetic-A Processor Architect's Perspective
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
Ruby B. Lee
ANCS
2007
ACM
13 years 11 months ago
Compiling PCRE to FPGA for accelerating SNORT IDS
Deep Payload Inspection systems like SNORT and BRO utilize regular expression for their rules due to their high expressibility and compactness. The SNORT IDS system uses the PCRE ...
Abhishek Mitra, Walid A. Najjar, Laxmi N. Bhuyan
VLSISP
2011
358views Database» more  VLSISP 2011»
13 years 2 months ago
Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition
Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from superlinear increases in ...
Karthik Nagarajan, Brian Holland, Alan D. George, ...
INFOCOM
2010
IEEE
13 years 5 months ago
Group Device Pairing based Secure Sensor Association and Key Management for Body Area Networks
Body Area Networks (BAN) is a key enabling technology in E-healthcare such as remote health monitoring. An important security issue during bootstrap phase of the BAN is to securely...
Ming Li, Shucheng Yu, Wenjing Lou, Kui Ren