Sciweavers

522 search results - page 87 / 105
» Fast Smith-Waterman hardware implementation
Sort
View
SIGMETRICS
2008
ACM
214views Hardware» more  SIGMETRICS 2008»
13 years 7 months ago
HMTT: a platform independent full-system memory trace monitoring system
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...
Yungang Bao, Mingyu Chen, Yuan Ruan, Li Liu, Jianp...
ISCA
2008
IEEE
113views Hardware» more  ISCA 2008»
14 years 2 months ago
A Two-Level Load/Store Queue Based on Execution Locality
Multicore processors have emerged as a powerful platform on which to efficiently exploit thread-level parallelism (TLP). However, due to Amdahl’s Law, such designs will be incr...
Miquel Pericàs, Adrián Cristal, Fran...
MSS
2003
IEEE
98views Hardware» more  MSS 2003»
14 years 29 days ago
A Performance Analysis of the iSCSI Protocol
Fibre channel has long dominated the realm of storage area networks (SAN’s). However, with increased development and refining, iSCSI is fast becoming an equal contender, which ...
Stephen Aiken, Dirk Grunwald, Andrew R. Pleszkun, ...
ASAP
2002
IEEE
170views Hardware» more  ASAP 2002»
14 years 20 days ago
Reviewing 4-to-2 Adders for Multi-Operand Addition
Recently there has been quite a number of papers discussing the use of redundant 4-to-2 adders for the accumulation of partial products in multipliers, claiming one type to be sup...
Peter Kornerup
CVPR
2009
IEEE
15 years 2 months ago
A Convex Relaxation Approach for Computing Minimal Partitions
In this work we propose a convex relaxation approach for computing minimal partitions. Our approach is based on rewriting the minimal partition problem (also known as Potts mode...
Thomas Pock (Graz University of Technology), Anton...