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INFOCOM
2000
IEEE
13 years 11 months ago
Fast and Scalable Priority Queue Architecture for High-Speed Network Switches
-In this paper, we present a fast and scalable pipelined priority queue architecture for use in high-performance switches with support for fine-grained quality of service (QoS) gu...
Ranjita Bhagwan, Bill Lin
RTAS
1997
IEEE
13 years 11 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
SIGMETRICS
1997
ACM
153views Hardware» more  SIGMETRICS 1997»
13 years 11 months ago
Queue Management for Explicit Rate Based Congestion Control
Rate based congestion control has been considered desirable, both to deal with the high bandwidth-delay products of today's high speed networks, and to match the needs of eme...
Qingming Ma, K. K. Ramakrishnan
AINA
2005
IEEE
14 years 1 months ago
3D-VOQ Switch Design and Evaluation
Input Buffered Switches with Virtual Output Queues(VOQ) design to avoid Head-Of-Line problems, is a primary design of switches that can be scalable to very high speeds. However, t...
Ding-Jyh Tsaur, Xian-Yang Lu, Chin-Chi Wu, Woei Li...
ANCS
2006
ACM
14 years 1 months ago
Localized asynchronous packet scheduling for buffered crossbar switches
Buffered crossbar switches are a special type of crossbar switches. In such a switch, besides normal input queues and output queues, a small buffer is associated with each crosspo...
Deng Pan, Yuanyuan Yang