49 search results - page 5 / 10 » Fast buffer insertion considering process variations |
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
- Dynamic power consumption in CMOS circuits is usually estimated based on the number of signal transitions. However, when considering glitches, this is not accurate because narrow...
SLIP
2009
ACM
14 years 1 months ago
2009
ACM
In this paper, a comprehensive and fast method is presented for the timing analysis of process variations on single-walled carbon nanotube (SWCNT) bundles. Unlike previous works t...
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
This paper investigates methods for minimizing the impact of process variation on clock skew using buffer and wire sizing. While most papers on clock trees ignore data-path circuit...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
JEI
2002
13 years 6 months ago
2002
The recent proliferation of digital multimedia content has raised concerns about authentication mechanisms for multimedia data. A number of authentication techniques based on digi...