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ICCD
2005
IEEE
131views Hardware» more  ICCD 2005»
14 years 5 months ago
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs
The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog ...
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
EDBT
2010
ACM
116views Database» more  EDBT 2010»
14 years 3 months ago
HARRA: fast iterative hashed record linkage for large-scale data collections
We study the performance issue of the “iterative” record linkage (RL) problem, where match and merge operations may occur together in iterations until convergence emerges. We ...
Hung-sik Kim, Dongwon Lee
DAC
2009
ACM
14 years 3 months ago
PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation
It is unknown how to include stochastic process variation into fast-multipole-method (FMM) for a full chip capacitance extraction. This paper presents a parallel FMM extraction us...
Fang Gong, Hao Yu, Lei He
CCGRID
2009
IEEE
14 years 3 months ago
Improving Parallel Write by Node-Level Request Scheduling
In a cluster of multiple processors or cpu-cores, many processes may run on each compute node. Each process tends to issue contiguous I/O requests for snapshot, checkpointing or s...
Kazuki Ohta, Hiroya Matsuba, Yutaka Ishikawa
ICC
2008
IEEE
199views Communications» more  ICC 2008»
14 years 3 months ago
Lower-Complexity Layered Belief-Propagation Decoding of LDPC Codes
Abstract— The design of LDPC decoders with low complexity, high throughput, and good performance is a critical task. A well-known strategy is to design structured codes such as q...
Yuan-Mao Chang, Andres I. Vila Casado, Mau-Chung F...