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ISCA
2002
IEEE
104views Hardware» more  ISCA 2002»
13 years 9 months ago
Speculative Dynamic Vectorization
Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also pre...
Alex Pajuelo, Antonio González, Mateo Valer...
IPPS
2010
IEEE
13 years 7 months ago
On the parallelisation of MCMC by speculative chain execution
Abstract--The increasing availability of multi-core and multiprocessor architectures provides new opportunities for improving the performance of many computer simulations. Markov C...
Jonathan M. R. Byrd, Stephen A. Jarvis, Abhir H. B...
PLDI
2010
ACM
14 years 2 months ago
Supporting speculative parallelization in the presence of dynamic data structures
The availability of multicore processors has led to significant interest in compiler techniques for speculative parallelization of sequential programs. Isolation of speculative s...
Chen Tian, Min Feng, Rajiv Gupta
MICRO
1995
IEEE
125views Hardware» more  MICRO 1995»
14 years 1 months ago
Disjoint eager execution: an optimal form of speculative execution
Instruction Level Parallelism (ILP) speedups of an order-of-magnitude or greater may be possible using the techniques described herein. Traditional speculative code execution is t...
Augustus K. Uht, Vijay Sindagi, Kelley Hall
MICRO
1993
IEEE
97views Hardware» more  MICRO 1993»
14 years 1 months ago
Register renaming and dynamic speculation: an alternative approach
In this paper, we present a novel mechanism that implements register renaming, dynamic speculation and precise interrupts. Renaming of registers is performed during the instructio...
Mayan Moudgill, Keshav Pingali, Stamatis Vassiliad...