22 search results - page 3 / 5 » Fault Grading FPGA Interconnect Test Configurations |
DFT
2002
IEEE
14 years 13 days ago
2002
IEEE
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
ERSA
2010
13 years 5 months ago
2010
SRAM-based FPGA devices are an attractive option for data processing on space-based platforms, due to high computational capabilities and a lower power envelope than traditional pr...
ACST
2006
13 years 9 months ago
2006
Adaptive fault isolation methods based on discrepancyenabled pairwise comparisons are developed for reconfigurable logic devices. By observing the discrepancy characteristics of m...
ETS
2007
IEEE
14 years 1 months ago
2007
IEEE
The paper proposes a new concept of diagnosing faulty links in Network-on-a-Chip (NoC) designs. The method is based on functional fault models and it implements packet address dri...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the developmen...