Yield enhancements of design-specific FPGAs

The high unit cost of FPGA devices often deters their use beyond the prototyping stage. Efforts have been made to reduce the part-cost of FPGA devices, resulting in the development of Design-Specific FPGAs. These parts offer cost reductions by limiting manufacturing tests and improving the number of working devices in a wafer. This paper addresses the issue of yield enhancement in Design-Specific FPGAs. In this paper, an analytical model predicting the probability of mapping a specific design onto potentially defective FPGAs is developed. When combined with existing yield modelling techniques, a quantitative measure of the potential yield improvements of the Design-Specific FPGA approach is reported for current and future technology nodes. It is found that this approach, while beneficial with current manufacturing technology, may not be suitable for 22nm technology or beyond. Categories and Subject Descriptors B.8.1 [Hardware]: Performance and Reliability--Reliability, Testing, and Fa...

• Type: Conference
• Year: 2006
• Where: FPGA
• Authors: Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko
• Keywords: Design-specific Fpga, FPGA, FPGA 2006, FPGA Devices