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ITC
2003
IEEE
127views Hardware» more  ITC 2003»
14 years 1 months ago
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects
In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic m...
Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting...
IWCMC
2009
ACM
14 years 2 months ago
On fault tolerant ad hoc network design
Minimal configuration and quick deployment of ad hoc networks make it suitable for numerous applications such as emergency situations, border monitoring, and military missions, e...
Wasim El-Hajj, Hazem Hajj, Zouheir Trabelsi
TC
2010
13 years 6 months ago
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
WADS
2009
Springer
223views Algorithms» more  WADS 2009»
14 years 2 months ago
Fault Tolerant External Memory Algorithms
Abstract. Algorithms dealing with massive data sets are usually designed for I/O-efficiency, often captured by the I/O model by Aggarwal and Vitter. Another aspect of dealing with ...
Gerth Stølting Brodal, Allan Grønlun...
BERTINORO
2005
Springer
14 years 1 months ago
Self-Management of Virtual Paths in Dynamic Networks
Abstract Virtual path management in dynamic networks poses a number of challenges related to combinatorial optimisation, fault and traffic handling. Ideally such management should ...
Poul E. Heegaard, Otto Wittner, Bjarne E. Helvik