—New methods for fault-effect propagation and state justification that use finite-state-machine sequences are proposed for sequential circuit test generation. Distinguishing se...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
Patrick Girard, Christian Landrault, Serge Pravoss...
Sequential test generators fail to yield tests for some stuck-at-faults because they are unable to reach certain states necessary for exciting propagating these target faults. Add...
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...
The problem of test generation belongs to the class of NP-complete problems and it is becoming more and more di cult as the complexity of VLSI circuits increases, and as long as e...
Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxen...