TCAD 1998 - PDF Preprint Papers

TCAD 1998

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TCAD
1998

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Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions

14 years 6 days ago

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— Ordered Kronecker functional decision diagrams (OKFDD’s) are a data structure for efﬁcient representation and manipulation of Boolean functions. OKFDD’s are a generalizat...

Rolf Drechsler, Bernd Becker

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Id	Views	Title	Status

1	161	Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions	claim
2	159	Code density optimization for embedded DSP processors using data compression techniques	claim
3	154	Address generation for memories containing multiple arrays	claim
4	127	Gate-level power estimation using tagged probabilistic simulation	claim
5	126	Iterative remapping for logic circuits	claim
6	125	Test-point insertion: scan paths through functional logic	claim
7	125	BDD-based synthesis of extended burst-mode controllers	claim
8	119	A controller redesign technique to enhance testability of controller-data path circuits	claim
9	115	Probabilistic modeling of dependencies during switching activity analysis	claim
10	114	Behavioral optimization using the manipulation of timing constraints	claim
11	110	Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG	claim
12	109	Diagnosing realistic bridging faults with single stuck-at information	claim
13	107	Optimizing dominant time constant in RC circuits	claim
14	102	A unified MOSFET channel charge model for device modeling in circuit simulation	claim
15	101	An efficient algorithm for performance-optimal FPGA technology mapping with retiming	claim
16	96	Diagnosis of clustered faults and wafer testing	claim
17	95	A framework for comparing models of computation	claim
18	95	High-precision interconnect analysis	claim
19	91	Cost-free scan: a low-overhead scan path design	claim
20	86	Fast heuristic and exact algorithms for two-level hazard-free logic minimization	claim
21	83	Telescopic units: a new paradigm for performance optimization of VLSI designs	claim
22	82	LOT: Logic Optimization with Testability. New transformations for logic synthesis	claim
23	82	Structural methods for the synthesis of speed-independent circuits	claim
24	81	Characterization and parameterized generation of synthetic combinational benchmark circuits	claim
25	65	Locating bridging faults using dynamically computed stuck-at fault dictionaries	claim

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