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» Fault Tolerance for Multistage Interconnection Networks
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ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
14 years 23 days ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...
IPPS
1997
IEEE
14 years 1 days ago
Nearly Optimal One-To-Many Parallel Routing in Star Networks
Star networks were proposedrecently as an attractive alternative to the well-known hypercube models for interconnection networks. Extensive research has been performed that shows ...
Chi-Chang Chen, Jianer Chen
MICRO
2010
IEEE
167views Hardware» more  MICRO 2010»
13 years 5 months ago
Erasing Core Boundaries for Robust and Configurable Performance
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
IPPS
2007
IEEE
14 years 2 months ago
RI2N/UDP: High bandwidth and fault-tolerant network for a PC-cluster based on multi-link Ethernet
PC-clusters with high performance/cost ratio have been one of the typical platforms for high performance computing. To lower costs, Gigabit Ethernet is often used for intercommuni...
Takayuki Okamoto, Shin'ichi Miura, Taisuke Boku, M...
HPCA
2008
IEEE
14 years 8 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler