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» Fault Tolerant Boolean Satisfiability
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ETS
2010
IEEE
150views Hardware» more  ETS 2010»
13 years 8 months ago
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs
It was shown in the past that ATPG based on the Boolean Satisfiability problem is a beneficial complement to traditional ATPG techniques. Its advantages can be observed especially ...
Daniel Tille, Stephan Eggersglüß, Rene ...
DAC
2008
ACM
14 years 8 months ago
The synthesis of robust polynomial arithmetic with stochastic logic
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
Weikang Qian, Marc D. Riedel
DSN
2011
IEEE
12 years 7 months ago
Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
Shuchang Shan, Yu Hu, Xiaowei Li
AAAI
2010
13 years 7 months ago
Computing Cost-Optimal Definitely Discriminating Tests
The goal of testing is to discriminate between multiple hypotheses about a system--for example, different fault diagnoses--by applying input patterns and verifying or falsifying t...
Anika Schumann, Jinbo Huang, Martin Sachenbacher
IPPS
1998
IEEE
13 years 11 months ago
An Efficient RMS Admission Control and Its Application to Multiprocessor Scheduling
A real-time system must execute functionally correct computations in a timely manner. In order to guarantee that all tasks accepted in the system will meet their timing requiremen...
Sylvain Lauzac, Rami G. Melhem, Daniel Mossé...