18 search results - page 3 / 4 » Fault Tolerant CMOS Logic Using Ternary Gates |
DAC
2009
ACM
14 years 10 months ago
2009
ACM
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
DSD
2004
IEEE
14 years 1 months ago
2004
IEEE
This paper describes the architecture of a safety system of the railway's interlocking equipment, which has been developed for Czech railways. The system will be used for the...
HASE
1998
IEEE
14 years 2 months ago
1998
IEEE
Fault trees provide a graphical and logical framework for analyzing the reliability of systems. A fault tree provides a conceptually simple modeling framework to represent the sys...
PRDC
2008
IEEE
14 years 4 months ago
2008
IEEE
Reliability has become a serious concern as systems embrace nanometer technologies. In this paper, we propose a novel approach for organizing redundancy that provides high degree ...
JOLPE
2010
13 years 8 months ago
2010
This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft e...