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132
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PLDI
1999
ACM
15 years 8 months ago
Cache-Conscious Structure Layout
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus
ICDCS
2008
IEEE
15 years 10 months ago
stdchk: A Checkpoint Storage System for Desktop Grid Computing
— Checkpointing is an indispensable technique to provide fault tolerance for long-running high-throughput applications like those running on desktop grids. This paper argues that...
Samer Al-Kiswany, Matei Ripeanu, Sudharshan S. Vaz...
129
Voted
SNPD
2003
15 years 5 months ago
Incomplete Information Processing for Optimization of Distributed Applications
This paper focuses on non-strict processing, optimization, and partial evaluation of MPI programs which use incremental data structures (ISs). We describe the design and implement...
Alfredo Cristóbal-Salas, Andrei Tchernykh, ...
117
Voted
DAC
2009
ACM
16 years 4 months ago
Energy-aware error control coding for Flash memories
The use of Flash memories in portable embedded systems is ever increasing. This is because of the multi-level storage capability that makes them excellent candidates for high dens...
Veera Papirla, Chaitali Chakrabarti
129
Voted
IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
15 years 10 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...