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» Fault emulation: a new approach to fault grading
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DATE
2007
IEEE
150views Hardware» more  DATE 2007»
14 years 2 months ago
A low-SER efficient core processor architecture for future technologies
Device scaling in new and future technologies brings along severe increase in the soft error rate of circuits, for combinational and sequential logic. Although potential solutions...
Eduardo Luis Rhod, Carlos Arthur Lang Lisbôa...
ICPPW
2003
IEEE
14 years 1 months ago
A Fault-tolerant Routing Strategy for Gaussian Cube Using Gaussian Tree
Gaussian Cubes (GCs) are a family of interconnection topologies in which the interconnection density and algorithmic efficiency are linked by a common parameter, the variation of ...
Loh Peter, Xinhua Zhang
IOLTS
2002
IEEE
148views Hardware» more  IOLTS 2002»
14 years 26 days ago
Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing
The reusing of the same hardware resources to implement speed-critical algorithms, without interrupting system operation, is one of the main reasons for the increasing use of reco...
Manuel G. Gericota, Gustavo R. Alves, Miguel L. Si...
APCSAC
2004
IEEE
13 years 11 months ago
A Compiler-Assisted On-Chip Assigned-Signature Control Flow Checking
As device sizes continue shrinking, lower charges are needed to activate gates, and consequently ever smaller external events (such as single ionizing particles of naturally occurr...
Xiaobin Li, Jean-Luc Gaudiot
JSA
2000
100views more  JSA 2000»
13 years 7 months ago
Stripped mirroring RAID architecture
Redundant arrays of independent disks (RAID) provide an ecient stable storage system for parallel access and fault tolerance. The most common fault tolerant RAID architecture is R...
Hai Jin, Kai Hwang