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» Fault tolerant nanoelectronic processor architectures
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IEEECIT
2010
IEEE
13 years 6 months ago
CFCSS without Aliasing for SPARC Architecture
With the increasing popularity of COTS (commercial off the shelf) components and multi-core processor in space and aviation applications, software fault tolerance becomes attracti...
Chao Wang, Zhongchuan Fu, Hongsong Chen, Wei Ba, B...
GI
2004
Springer
14 years 26 days ago
Towards a Framework and a Design Methodology for Autonomic Integrated Systems
: The transition from microelectronics to nanoelectronics reaches physical limits and results in a paradigm shift in the design and fabrication of electronic circuits. The conserva...
Andreas Herkersdorf, Wolfgang Rosenstiel
DAC
2002
ACM
14 years 8 months ago
Software-based diagnosis for processors
Software-based self-test (SBST) is emerging as a promising technology for enabling at-speed test of high-speed microprocessors using low-cost testers. We explore the fault diagnos...
Li Chen, Sujit Dey
CASES
2009
ACM
14 years 2 months ago
Towards scalable reliability frameworks for error prone CMPs
As technology scales and the energy of computation continually approaches thermal equilibrium [1,2], parameter variations and noise levels will lead to larger error rates at vario...
Joseph Sloan, Rakesh Kumar
DFT
1994
IEEE
121views VLSI» more  DFT 1994»
13 years 11 months ago
Reconfiguration in 3D Meshes
The 1: track model for fault tolerant 2 0 processor arrays is extended to 30 mesh architectures. Non-intersecting, continuous, straight and non-near miss compensation paths are co...
Anuj Chandra, Rami G. Melhem